Four sigil-kernel commits advance the HAL arch matrix from 0x51E000 to 0x525000, adding 8 seams: Apple GXF UltraFusion cross-fabric, G3 L2CR cache controller, Apple BCM4388 Bluetooth/BLE HCI link, G4 7450 L2+L3 dual cache controller, Apple ANS3 NVMe controller, G3/G4 ATA UDMA bus master, Apple M-series Gen4 PCIe root complex, and G5 K2/Shasta PCI-X bus controller.
deb5be5 — GXF + G3 L2CR
apple_gxf.sg
0x51E000GPU Cross-Fabric / UltraFusion QoS (dual-die QoS weights, inter-die transfer counters, BW estimation). GXF (GPU Cross-Fabric) is the UltraFusion die-interconnect bus in Apple Silicon M-Ultra SoCs, coupling two M-Max dies. It provides QoS weight programming (prioritising GPU, ANE, or CPU traffic across the fabric) and per-fabric / inter-die transfer counters for bandwidth estimation.
gxf_init(version): initialises GXF with version string; zeros all state. gxf_qos_set(agent, weight): sets the QoS weight for agent (GPU=0, ANE=1, CPU=2) — weight is a relative priority value (0–255). gxf_transfer(fabric, bytes): records a cross-fabric transfer on fabric (0=die0→die1, 1=die1→die0); increments xfr_count[fabric]; adds bytes to xfr_bytes[fabric]. gxf_interdie_transfer(bytes): records an inter-die transfer (UltraFusion link); increments interdie_count; adds bytes to interdie_bytes. gxf_bw_estimate(): returns a bandwidth estimate (total bytes transferred across all fabrics). gxf_qos_weight(agent) / gxf_xfr_count(fabric) / gxf_interdie_count(): accessors. GXF init=1 qos=1 xfr=1 K.ppc_l2ctrl.sg
0x51F000G3 L2CR cache controller (256/512/1024KB probe, bus ratio, ECC, flush, hit/miss proxy). The L2CR (L2 Cache Control Register) on G3 PowerPCs controls the external L2 cache — it is a single 32-bit register that sets cache size, bus-to-core speed ratio, ECC enablement, and cache enable/disable.
l2ctrl_init(): zeros state; clears l2_enabled. l2ctrl_probe_size(): probes the L2 cache size (returns 256, 512, or 1024 KB based on hardware). l2ctrl_set_bus_ratio(ratio): sets the bus-to-cache speed ratio (e.g., 2:1, 5:2). l2ctrl_ecc_enable(v): sets/clears the ECC enable gate. l2ctrl_enable(): enables the L2 cache; sets l2_enabled=1. l2ctrl_disable(): disables the L2 cache; sets l2_enabled=0. l2ctrl_flush(): performs a hardware flush; increments flush_count. l2ctrl_cache_hit() / l2ctrl_cache_miss(): hit/miss proxy — increment respective counters. l2ctrl_enabled() / l2ctrl_size_kb() / l2ctrl_flush_count() / l2ctrl_hits(): accessors. L2C init=1 ena=1 hit=1 K.3461943 — BCM4388 BT/BLE HCI + G4 7450 dual cache
apple_btconn.sg
0x520000BCM4388 Bluetooth/BLE HCI link (BR/EDR + BLE peer tables, HCI cmd/event ring, ACL TX/RX, BLE advert). The BCM4388 is a combined Wi-Fi/BT/BLE chip in Apple devices.
btconn_init(): zeros all state. btconn_bredr_connect(peer_slot, bd_addr): connects a BR/EDR (Classic Bluetooth) peer at peer_slot; sets bredr_peer[peer_slot].active=1, stores bd_addr. btconn_ble_connect(peer_slot, bd_addr): connects a BLE peer at peer_slot; sets ble_peer[peer_slot].active=1. btconn_bredr_disconnect(peer_slot) / btconn_ble_disconnect(peer_slot): clear respective peer slot. btconn_hci_cmd(opcode, params): enqueues an HCI command onto the HCI command ring; increments hci_cmd_count. btconn_hci_event(event_code): records an incoming HCI event; increments hci_event_count. btconn_acl_tx(peer_slot, bytes): transmits an ACL data packet; increments acl_tx_count and acl_tx_bytes. btconn_acl_rx(peer_slot, bytes): receives an ACL data packet; increments acl_rx_count. btconn_ble_advertise(): sends a BLE advertisement; increments ble_adv_count. btconn_bredr_peer_active(slot) / btconn_acl_tx_count() / btconn_ble_adv_count(): accessors. BTC init=1 con=1 acl=1 K.ppc_7450_caches.sg
0x521000G4 7450/7455/7457 L2+L3 dual cache controller (256KB L2 + up to 2MB L3, per-cache ECC, flush, hit/miss). The G4 7450 "Voyager" family (7450, 7455, 7457) has an on-die 256KB L2 cache and a separate backside L3 bus supporting up to 2MB of external L3 SRAM.
g4l_init(): zeros state. g4l_l2_enable(size_kb): enables the L2 cache with size_kb = 256; sets l2_enabled. g4l_l3_enable(size_mb): enables the external L3 cache with size_mb (0, 1, or 2 MB); sets l3_enabled. g4l_l2_ecc_enable(v) / g4l_l3_ecc_enable(v): sets/clears per-cache ECC gates. g4l_l2_flush() / g4l_l3_flush(): hardware flush; increment respective flush_count. g4l_l2_hit() / g4l_l2_miss() / g4l_l3_hit() / g4l_l3_miss(): hit/miss proxy — increment counters. g4l_l2_enabled() / g4l_l3_size_mb() / g4l_l2_flush_count() / g4l_l2_hits(): accessors. G4L init=1 ena=1 hit=1 K.9cd0599 — ANS3 NVMe + G3/G4 ATA UDMA bus master
apple_nvme.sg
0x522000Apple NVMe (ANS3) controller (namespace enum, admin+I/O queues, read/write/trim, MB accounting, power state). ANS3 (Apple NVMe Storage) is the custom NVMe controller in Apple Silicon — it provides a proprietary register interface over the PCIe fabric to the internal SSD.
nvme_init(): zeros state; clears all queues. nvme_namespace_enumerate(): enumerates NVMe namespaces; increments namespace_count. nvme_admin_cmd(opcode, len): sends an admin queue command (Identify, Get Log Page, etc.); increments admin_cmd_count. nvme_io_queue_create(depth): creates an I/O queue pair (submission + completion) with depth entries; increments io_queue_count. nvme_read(ns, lba, blocks, mb): dispatches a read I/O; increments read_count; adds mb to read_mb. nvme_write(ns, lba, blocks, mb): dispatches a write I/O; increments write_count; adds mb to write_mb. nvme_trim(ns, lba, blocks): dispatches a deallocate (TRIM/UNMAP) I/O; increments trim_count. nvme_power_state(ps): sets the NVMe power state (0=fully operational, 1=low-power, 2=off). nvme_read_mb() / nvme_write_mb() / nvme_io_queue_count() / nvme_power_state_val(): accessors. NVM init=1 rw=1 pow=1 K.ppc_ata_bm.sg
0x523000G3/G4 ATA UDMA bus master DMA (dual-channel device bitmask, PRD-based DMA read/write, sector+IRQ counters). The ATA UDMA bus master on G3/G4 PowerMacs (integrated in the Keylargo MAC-I/O or K2 south bridge) handles DMA for ATA/ATAPI drives via Physical Region Descriptor (PRD) tables.
ata_bm_init(): zeros state. ata_bm_attach(channel, device): attaches an ATA device (device 0=master, 1=slave) on channel 0 or 1; sets the corresponding bit in device_bitmask. ata_bm_dma_read(channel, sectors, prd_count): performs a PRD-based DMA read — sectors sectors transferred, using prd_count PRD entries; increments dma_read_count; adds sectors to sector_count. ata_bm_dma_write(channel, sectors, prd_count): PRD-based DMA write; increments dma_write_count. ata_bm_irq(channel): records an ATA interrupt for channel; increments irq_count. ata_bm_device_bitmask() / ata_bm_sector_count() / ata_bm_dma_read_count() / ata_bm_irq_count(): accessors. ATB init=1 att=1 dma=1 K.1e78e80 — M-series Gen4 PCIe root complex + G5 PCI-X bus controller
apple_pcie.sg
0x524000M-series Gen4 PCIe root complex (4-port enable/detect, config R/W, BAR mapping, DMA, MSI routing, ASPM). The Apple Silicon PCIe root complex provides 4 Gen4 lanes, each configurable as a separate root port.
pcie_init(): zeros state. pcie_port_enable(port): enables PCIe root port port (0–3); sets port_enabled[port]=1. pcie_port_detect(port, link_speed_gen): detects a device on port at link speed Gen1/2/3/4; sets port_link[port].up=1, stores link_speed. pcie_config_read(port, devfn, reg): reads a PCIe config space register; increments config_read_count. pcie_config_write(port, devfn, reg, val): writes config space; increments config_write_count. pcie_bar_map(port, bar_idx, pa, size_mb): maps a BAR to physical address pa with size_mb aperture; stores in bar_map[port][bar_idx]. pcie_dma(port, bytes): records a DMA transfer; increments dma_count. pcie_msi_route(port, vector): routes an MSI interrupt; increments msi_count. pcie_aspm_enter(port, state): records ASPM entry (L0s=1, L1=2); increments aspm_entry_count. pcie_port_up(port) / pcie_dma_count() / pcie_msi_count() / pcie_aspm_count(): accessors. PCE init=1 prt=1 dma=1 K.ppc_pcix.sg
0x525000G5 K2/Shasta PCI-X 133MHz bus controller (6-slot device enum, config R/W, DMA byte tracking, IRQ routing). The G5 K2/Shasta south bridge includes a PCI-X 133MHz host controller providing 6 device slots, config space access, DMA, and IRQ routing to the K2-PIC.
pcix_init(): zeros state. pcix_enumerate(): enumerates up to 6 PCI-X slots; stores device_count. pcix_config_read(slot, reg): reads a PCI-X config register for slot (0–5); increments config_reads. pcix_config_write(slot, reg, val): writes config space; increments config_writes. pcix_dma(slot, bytes): records a DMA transfer from slot; increments dma_count; adds bytes to dma_bytes. pcix_irq_route(slot, vec): routes an IRQ for slot to the K2-PIC vector vec; increments irq_count. pcix_device_count() / pcix_dma_bytes() / pcix_config_reads() / pcix_irq_count(): accessors. PXB init=1 dev=1 dma=1 K.Arch matrix summary
| Commit | Seam | Address | Hardware |
|---|---|---|---|
deb5be5 | apple_gxf.sg | 0x51E000 | Apple GXF UltraFusion cross-fabric QoS |
deb5be5 | ppc_l2ctrl.sg | 0x51F000 | G3 L2CR cache controller |
3461943 | apple_btconn.sg | 0x520000 | BCM4388 Bluetooth/BLE HCI link |
3461943 | ppc_7450_caches.sg | 0x521000 | G4 7450 L2+L3 dual cache controller |
9cd0599 | apple_nvme.sg | 0x522000 | Apple ANS3 NVMe controller |
9cd0599 | ppc_ata_bm.sg | 0x523000 | G3/G4 ATA UDMA bus master DMA |
1e78e80 | apple_pcie.sg | 0x524000 | M-series Gen4 PCIe root complex |
1e78e80 | ppc_pcix.sg | 0x525000 | G5 K2/Shasta PCI-X 133MHz bus controller |
Arch matrix now at 0x525000. Batch 18 closes the storage, cache, BT/wireless, and interconnect clusters for both the Apple Silicon and legacy PowerPC sides of the HAL. The 0.7.0 kernel HAL sprint continues.