← Blog
0.7.0 · KERNEL · HAL

HAL Batch 16 — AirPlay/MAC-IO + Handoff/Rage128 + BootPolicy/970MP (sigil-kernel 9dfdf07→c953c83)

June 23, 2026 · sigil-kernel 9dfdf07 + 27bb229 + c953c83 · Sigil-Docs
kernel hal apple-silicon powerpc hardware 0.7.0

Three sigil-kernel commits extend the HAL arch matrix from 0x510000 to 0x515000, adding 6 seams: Apple AirPlay 2 receiver sink, G4 Keylargo MAC-I/O hub, Apple Handoff/Continuity, ATI Rage 128 GPU, Apple Boot Policy Engine, and PowerPC 970MP dual-core SMP controller.


9dfdf07 — AirPlay 2 receiver + G4 MAC-I/O

apple_airplay.sg
0x510000
AirPlay 2 sink (RTSP session, RTP counters, 80ms jitter buffer, MediaRemote). airplay_init(): zeros state. airplay_session_open(audio_codec, video_codec): opens an RTSP session — sets AUDIO_SINK=1 if audio codec present, VIDEO_SINK=1 if video codec present; records codec IDs. airplay_session_close(): clears session state. airplay_rtp_packet(bytes): receives an RTP packet; increments pkt_count and bytes_count; models the 80ms jitter buffer (accumulates jitter_buf_ms += 20 per packet, caps at 80ms). airplay_media_play() / airplay_media_pause() / airplay_media_skip(): MediaRemote control events — increment respective counters. airplay_audio_sink() / airplay_video_sink() / airplay_pkt_count() / airplay_jitter_ms(): accessors. ARP init=1 ses=1 pkt=1 K.
ppc_macio.sg
0x511000
G4 Keylargo MAC-I/O (Heathrow/Keylargo/Pangea variants, GPIO/UART/I2S/VIA). The MAC-I/O ASIC (Heathrow on G3, Keylargo and Pangea on G4) integrates GPIO, dual UART (serial ports), I2S audio, and the VIA/CUDA ADB keyboard/mouse controller. macio_init(variant): initialises for variant (0=Heathrow, 1=Keylargo, 2=Pangea). macio_gpio_dir(pin, dir): sets direction of GPIO pin (0=input, 1=output) via shadow register. macio_gpio_write(pin, val): writes 0 or 1 to an output GPIO pin. macio_gpio_read(pin): reads an input GPIO pin. macio_uart_tx(channel, byte): transmits a byte on UART channel 0 or 1; increments uart_tx_count[channel]. macio_i2s_frame(): advances the I2S audio frame counter. macio_via_cmd(cmd): sends a VIA/CUDA command; increments via_cmd_count. macio_irq_dispatch(vec): dispatches an IRQ from the MAC-I/O IRQ controller; increments irq_count. MIO init=1 gio=1 i2s=1 K.

27bb229 — Handoff/Continuity + ATI Rage 128

apple_handoff.sg
0x512000
Handoff/Continuity bridge (8-slot peer table, BLE adv, Safari/Mail/Call, offer/accept/complete). Handoff lets the user switch ongoing activities (Safari tabs, Mail drafts, phone calls) between Apple devices. handoff_init(): zeros state; initialises 8-slot peer table. handoff_ble_advertise(activity_type, token): broadcasts a BLE advertisement for activity_type (Safari=0, Mail=1, Call=2) with an activity token; increments adv_count. handoff_offer(peer_slot, activity_type, token): offers an activity to a peer at peer_slot; sets the state machine to OFFERED. handoff_accept(peer_slot): peer accepts the offer; sets state to ACCEPTED. handoff_complete(peer_slot): activity transfer completes; increments xfr_count; adds payload_kb to wifi_payload_kb (Wi-Fi payload used to transfer the activity state). handoff_peer_state(slot): returns the state machine value for slot (IDLE/OFFERED/ACCEPTED/COMPLETE). HOF init=1 adv=1 xfr=1 K.
ppc_rage128.sg
0x513000
ATI Rage 128 GPU (mode-set, 2D BitBLT + solid fill, VSync, FIFO). The ATI Rage 128 was the GPU in late-G3 and early-G4 PowerMacs (Power Mac G4 AGP/Gigabit Ethernet). It provides 2D acceleration and basic 3D. rage128_init(): zeros state; clears ACCEL_EN. rage128_mode_set(width, height, depth, pitch): sets the display mode — stores w, h, depth (16 or 32 bpp), and pitch (bytes per scanline). rage128_accel_enable(v): sets/clears ACCEL_EN. rage128_blit(sx, sy, dx, dy, w, h): 2D BitBLT operation (source-to-destination rectangle copy); increments blt_count. rage128_fill(x, y, w, h, color): solid-fill rectangle; increments fill_count. rage128_vsync(): VSync event; increments vsync_count. rage128_fifo_depth(d): sets the FIFO depth. rage128_accel_en() / rage128_blt_count() / rage128_vsync_count(): accessors. R28 init=1 mde=1 blt=1 K.

c953c83 — Boot Policy Engine + 970MP dual-core

apple_bootpol.sg
0x514000
Boot Policy Engine (Full/Reduced/Permissive security, signed object gate, MDM, nonce). The Boot Policy Engine enforces the boot security policy on Apple Silicon Macs, analogous to the T2's secure boot policy on Intel Macs. bootpol_init(): sets security_level=FULL (most restrictive). bootpol_set_level(level): sets security level — FULL=0 (only Apple-signed software), REDUCED=1 (allows notarised third-party kernels with a one-time downgrade), PERMISSIVE=2 (unsigned allowed — development mode); increments policy_change_count (audit log). bootpol_check_object(signed): gate check — signed=1 is always allowed; signed=0 (unsigned object) is allowed only if security_level == PERMISSIVE, else denied; increments check_count. bootpol_enroll_mdm(ok): MDM enrolment — if ok=1 sets mdm_enrolled=1. bootpol_nonce_valid(nonce): validates a boot nonce — returns 1 if nonce != 0. bootpol_check_count() / bootpol_policy_change_count() / bootpol_mdm_enrolled(): accessors. BPE init=1 chk=1 pol=1 K.
ppc_970mp.sg
0x515000
PowerPC 970MP dual-core SMP controller (core state machine, IPI, MP_SYNC). The 970MP is IBM's dual-core PowerPC 970 (used in the Power Mac G5 Quad, 2005). mp_init(): initialises both cores — core0 = RUNNING, core1 = HALTED. mp_kick_secondary(): kicks core1 from HALTED to RUNNING; sets core1_state=RUNNING. mp_sync(flag): sets/clears the MP_SYNC flag (used for inter-core barrier synchronisation — both cores check this flag before proceeding past a sync point). mp_ipi_send(src_core, dst_core): sends an inter-processor interrupt from src_core to dst_core; increments ipi_send_count. mp_ipi_ack(core): acknowledges receipt of an IPI on core; increments ipi_ack_count. mp_insn_count(core, n): increments the instruction count proxy for core by n. mp_core_running(core) / mp_ipi_send_count() / mp_insn_count_core(core): accessors. MPC init=1 smp=1 ipi=1 K.

Arch matrix now at 0x515000.