VGA CRTC + DAC Drivers — 14 x86 Drivers, Complete VGA Subsystem

The VGA subsystem is complete. Two new drivers ship in this batch: the VGA 6845 CRTC driver (cursor, start-address scroll, display/vsync status, 80-column mode 3 verified) and the VGA DAC palette driver (256-entry 6-bit RGB, CGA-standard color 7, CTL_SET_COLOR/GET_COLOR/BLANK/UNBLANK). Together with the Bochs BGA driver (post-BIOS GOP), sigilOS now has a complete three-layer x86 display stack: mode-set → raster timing → color output. Total: 14 verified x86 drivers. (sigil-drivers 4188d1a, 2c63577)

sigilOS desktop — Lumen with complete VGA display stack — sigilOS desktop running with the complete VGA display stack: BGA mode-set + CRTC raster + DAC palette

VGA 6845 CRTC driver

Commit 4188d1a. Driver: drivers/display/vga-crtc. State at 0x8F0000. CLS class: CLS_DISPLAY.

The Motorola 6845 CRT Controller is the core of the IBM VGA standard and its MDA/CGA predecessors. It controls raster scan timing, cursor position, and display start address — the three things that determine what appears on screen and where the cursor blinks.

I/O layout: MISC register (0x3C2 write / 0x3CC read) — bit0 is the CGA-compatible I/O select. When set, the CRTC index register sits at 0x3D4 and the data register at 0x3D5. Live QEMU: MISC=0x01 (CGA-compat active).
CRTC registers (accessed via index/data pair at 0x3D4/0x3D5): H_TOTAL (0x00), CURSOR_HI (0x0E), CURSOR_LO (0x0F), START_HI (0x0C), START_LO (0x0D). Live QEMU: H_TOTAL=0x5F=95 — standard 80-column mode 3 horizontal total.
Cursor: crtc_cursor_set(offset) writes CURSOR_HI/CURSOR_LO as a character-cell offset into the text framebuffer. crtc_cursor_hide() sets bit5 of the cursor-start register (the "cursor off" bit defined in the 6845 spec); crtc_cursor_show() clears it. Tested: offset=160 read/write round-trip.
Scroll: crtc_scroll(offset) writes START_HI/START_LO to set the display start address. The CRTC begins its raster scan at this character-cell offset, making the display appear to scroll. Tested: offset=80 (scroll one text row = 80 characters).
Status: INPUT_STATUS1 (0x3DA): bit0 = display_enable (set during active display period), bit3 = vsync (set during vertical sync). Live QEMU: STATUS1=0x09 (both display_enable and vsync asserted).
Probe: crtc_probe reads MISC bit0 — set means CGA-compat I/O is active (normal VGA mode). This is the canonical probe path for the 6845 on VGA hardware.

CLS_DISPLAY dispatcher: CTL_CURSOR_GET / CTL_CURSOR_SET / CTL_CURSOR_HIDE / CTL_CURSOR_SHOW / CTL_SCROLL.

VGA DAC palette driver

Commit 2c63577. Driver: drivers/display/vga-dac. State at 0x900000. CLS class: CLS_DISPLAY.

The VGA palette DAC converts 8-bit color indices to physical RGB output. In VGA text mode and 256-color graphics modes, every pixel is an 8-bit index into this 256-entry table; the DAC performs the lookup to produce analog RGB voltages. Each entry holds R/G/B values at 6-bit resolution (0–63), giving 18-bit color depth in total.

I/O layout: DAC write index (0x3C8), DAC data (0x3C9, auto-advance through R/G/B components), DAC read index (0x3C7), pixel mask (0x3C6).
Write path: set index via 0x3C8, then write R, G, B as three sequential bytes to 0x3C9. After each group of three writes, the DAC auto-advances to the next palette index — so writing all 256 entries requires one index write followed by 768 data writes.
Read path: set index via 0x3C7, then read R, G, B as three sequential bytes from 0x3C9.
Pixel mask (0x3C6): an AND-mask applied to every pixel value before the DAC lookup. The standard value is 0xFF (pass all 8 bits). Write-only in QEMU (reads always return 0); dac_probe uses a DAC entry read/write round-trip instead of the pixel mask for detection.
Live QEMU verification: Color 0 (black) = (0, 0, 0). Color 7 (CGA light gray) = (42, 42, 42). DAC entry 200 r/w round-trip: write (10, 20, 30), read back (10, 20, 30). All three match.
BLANK/UNBLANK: CTL_BLANK writes 0x00 to the pixel mask register, masking all color indices to 0 (black output). CTL_UNBLANK restores 0xFF. This is the standard VGA blanking mechanism used during mode switches and screen saver activation.

CLS_DISPLAY dispatcher: CTL_SET_COLOR / CTL_GET_COLOR / CTL_BLANK / CTL_UNBLANK.

The complete VGA display stack

With both drivers verified, sigilOS has full programmatic control over every layer of the IBM VGA pipeline. The three drivers compose into a complete stack:

Layer	Driver	State addr	What it controls
DAC	`vga-dac`	`0x900000`	256-entry palette, physical RGB output
CRTC	`vga-crtc`	`0x8F0000`	Raster timing, cursor position, display scroll
Mode-set	`bga`	`0x890000`	Resolution + color depth (post-BIOS GOP)

The kernel can now: set a native resolution via BGA → configure the raster via CRTC → program the 256-color palette via DAC → display text or graphics. The full VGA pipeline from scan timing to color output is under Sigil-level control. No BIOS calls needed after initial boot — the drivers own the hardware directly.

Complete x86 driver inventory — 14 verified

All 14 drivers verified on live QEMU via x86-runverify.

Driver	I/O Ports	CLS Class	State
Intel 8253/8254 PIT	`0x40–0x43`	`CLS_TIME`	`0x820000`
Intel 8259A PIC	`0x20+0xA0`	`CLS_IRQ`	`0x830000`
Intel 8237A DMA	`0x00–0x0F`	`CLS_DMA`	`0x840000`
NS16550A UART COM1	`0x3F8`	`CLS_SERIAL`	`0x850000`
PS/2 i8042	`0x60+0x64`	`CLS_INPUT`	`0x860000`
MC146818A RTC	`0x70+0x71`	`CLS_TIME`	`0x870000`
PCI Config Space	`0xCF8+0xCFC`	`CLS_BUS_PCI`	`0x880000`
Bochs BGA	`0x1CE+0x1CF`	`CLS_DISPLAY`	`0x890000`
QEMU fw-cfg	`0x510+0x511`	`CLS_PLATFORM`	`0x8A0000`
PC Speaker	`0x61`	`CLS_AUDIO`	`0x8C0000`
Intel 82077AA FDC	`0x3F0–0x3F7`	`CLS_STORAGE`	`0x8D0000`
PC Parallel LPT1	`0x378–0x37A`	`CLS_CHAR`	`0x8E0000`
VGA 6845 CRTC	`0x3D4+0x3D5`	`CLS_DISPLAY`	`0x8F0000`
VGA DAC Palette	`0x3C7–0x3C9`	`CLS_DISPLAY`	`0x900000`

The state address space runs contiguously from 0x820000 (PIT) through 0x900000 (DAC), covering all 14 x86 platform devices. The three CLS_DISPLAY drivers — BGA, CRTC, DAC — span 0x890000–0x900000, the top of the current x86 driver block.