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HAL Batch 3 — Apple USB4/Media/ISP + PPC BAT/SMU/OHCI Seams (sigil-kernel 2206ac9→ba2498d)

June 22, 2026 · sigil-kernel 2206ac9 + 5e793b8 + ba2498d · Sigil-Docs
kernel hal apple-silicon powerpc hardware 0.7.0

Three more sigil-kernel commits push the arch matrix from 0x4C6000 to 0x4CB000, adding 6 HAL seams: Apple USB4/Thunderbolt 4, PPC Block Address Translation registers, Apple media encoder/decoder (H.264/HEVC/AV1/VP9/ProRes), G5 System Management Unit, Apple ISP (FaceTime HD / Center Stage), and PPC OHCI USB 1.1. All pass QEMU INIT tests.


2206ac9 — USB4/TB4 + PPC BAT

apple_usb4.sg
(0x4C6000)
USB4/Thunderbolt 4 host controller (2 ports). 2-port USB4/TB4 host. Per-port state: mode (USB=0/TB4=1/Alt-DP=2/PCIe=3), speed (byte at offset 4), tunnel bitmask (byte at offset 5 — bit 0=USB, bit 1=DP, bit 2=PCIe). usb4_attach(port, mode, speed): sets port mode + speed. usb4_tunnel_set(port, tunnel_bits): enables tunnel types on the port. usb4_dp_assign(port, lanes): assigns DisplayPort lanes (1 or 2) to the port; sets Alt-DP mode. usb4_pcie_assign(port): assigns PCIe tunnel; sets PCIe mode. usb4_active_count(): counts active ports. Note: 2206ac9 fixed a SPEED/TUNNEL byte overlap — both are now byte-sized at distinct offsets 4 and 5. USB4 init=1 con=1 tb4=1 K.
ppc_bats.sg
(0x4C7000)
PPC Block Address Translation register table. Block Address Translation (BAT) registers are the PowerPC virtual-to-physical address mapping mechanism for large regions (used for device I/O and the kernel text segment). 8 IBAT (instruction BAT) + 8 DBAT (data BAT) entries × 16B each at BAT_BASE = 0x4C7000. Each entry: virt:u32 (virtual address base), phys:u32 (physical address base), blksz:u32 (block size in bytes), flags:u8 (PP/WIMG bits). ibat_set(n, virt, phys, blksz, flags) / dbat_set(n, virt, phys, blksz, flags): write entry N. dbat_translate(virt): walks DBAT0–7 to find a match, returns physical address or -1 on miss. Boot preset via bats_preset_boot(): DBAT0 = ROM 0x20000000, 256MB, read-only; clears all other slots. Note: 2206ac9 fixed a signed overflow — 0xF0000000 is negative in Sigil i32; test redesigned to use the safe 0x20000000 range, and DBAT0 shadowing issue resolved. BAT init=1 set=1 xlat=1 K.

5e793b8 — Media encoder/decoder + G5 SMU

apple_media_enc.sg
(0x4C8000)
H.264/HEVC/AV1/VP9/ProRes hardware codec. Apple Silicon's media engine handles H.264, HEVC (H.265), AV1, VP9, and ProRes in hardware. 8 encode+decode slots. media_alloc_enc(codec, quality): allocates an encode slot for the given codec (0=H264/1=HEVC/2=AV1/3=VP9/4=ProRes) and quality preset (0=low/1=medium/2=high). media_alloc_dec(codec): allocates a decode slot. media_done(slot): marks slot complete. media_error(slot): marks slot errored; records error code. media_release(slot): frees the slot. media_active_count(): counts active slots. Quality presets: low=faster-encode, high=better-compression. MEN init=1 enc=1 dec=1 K.
ppc_smu.sg
(0x4C9000)
G5 PowerMac System Management Unit. The SMU is the power/fan/sleep/RTC coordinator on the PowerMac G5. smu_init(): sends READY probe (cmd=0x00), waits for ACK; sets SMU_READY flag. Guard: all other commands check SMU_READY and return SMU_ERR_NOTREADY if not set. smu_fan_set(fan_id, rpm): sends fan RPM command (cmd=0x08); fan_id 0 = front/intake, 1 = rear/exhaust. smu_sleep_arm(): sends sleep-arm command — the G5 will sleep on the next sleep trigger. smu_wake(): sends wake command. smu_rtc_write(mac_epoch_secs): writes Mac-epoch timestamp (seconds since Jan 1 1904) to the SMU RTC via cmd=0x5D. SMU init=1 fan=1 slp=1 K.

ba2498d — Apple ISP + PPC OHCI

apple_isp.sg
(0x4CA000)
Image Signal Processor (FaceTime HD / Center Stage). Apple Silicon ISP handles the FaceTime HD camera pipeline (demosaic, tone mapping, face detection for Center Stage). isp_power_on(): sends power-on command to the ISP co-processor, waits for READY ACK. isp_stream_start(): starts the capture stream — ISP begins filling frame slots. isp_stream_stop(): stops stream. 4 frame slots × 16B each. isp_frame_fill(slot): marks slot as being filled by the ISP. isp_frame_take(slot): caller marks slot as taken (frame ready for consumption). isp_frame_release(slot): releases slot back to the ISP for reuse. Frame lifecycle: ISP fills → caller takes → caller releases → ISP refills. ISP init=1 str=1 frm=1 K.
ppc_ohci.sg
(0x4CB000)
OHCI USB 1.1 host controller. OHCI (Open Host Controller Interface) is the USB 1.1 host controller standard used on PPC Power Macs (G3/G4 via Opti/NEC chips, G5 via OHCI on the U3 HT bus). Register set: HcControl, HcCommandStatus, HcInterruptStatus. 2-port hub model. ohci_start(): writes the USB operational state to HcControl. ohci_reset(): writes HCRESET bit to HcCommandStatus, polls until clear. ohci_port_connect(port, speed): records port connected + speed (full-speed=0, low-speed=1) in the port table. ohci_port_disconnect(port): clears port entry. ohci_intr_status(): reads HcInterruptStatus (root hub status change bit). OHC init=1 prt=1 rst=1 K.

Arch matrix now at 0x4CB000. Batch 3 brings the running HAL seam count past 30 for the Apple/PPC arch pair.